`include "defines.v"

module if_id (
    input wire                              clk,
    input wire                              rst,

    input wire                              stall_i,
    input wire                              flush_i,

    input wire [`RAM_ADDR_WIDTH - 1 : 0]    inst_addr_i,
    input wire [`INST_WIDTH - 1: 0]         inst_i,

    output reg [`RAM_ADDR_WIDTH - 1 : 0]    inst_addr_o,
    output reg [`INST_WIDTH - 1: 0]         inst_o
);

    always @(posedge clk) begin
        if(rst == 1'b1) begin
            inst_addr_o <= 0;
            inst_o      <= 0;
        end
        else begin
            if(stall_i == 1'b1) begin
                inst_addr_o <= inst_addr_o;
                inst_o      <= inst_o;
            end
            else if(flush_i == 1'b1) begin
                inst_addr_o <= 0;
                inst_o      <= 0;
            end
            else begin
                inst_addr_o <= inst_addr_i;
                inst_o      <= inst_i;
            end
        end
        
    end
endmodule
